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This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register. By continuing to use this site, you are consenting to our use of cookies. Accept Learn more…. DMA2 Channel2 global flag. DMA2 Channel2 transfer error flag. DMA2 Channel3 global flag. DMA2 Channel3 transfer error flag. DMA2 Channel4 global flag. DMA2 Channel4 transfer error flag. DMA2 Channel5 global flag.

DMA2 Channel5 transfer error flag. This parameter can be any combination for the same DMA of the following values:. DMA2 Channel4 half transfer interrupt. DMA2 Channel5 transfer error. Specifies the EXTI lines to be enabled or disabled. Specifies the mode for the EXTI lines. Specifies the trigger signal active edge for the EXTI lines.

Specifies the new state of the selected EXTI lines. UM 8. For the internal interrupt, the trigger selection is not needed the active edge is always the rising one. Interrupts and flags management functions This section provides functions allowing to configure the EXTI Interrupts sources and check or clear the flags or pending bits status.

These functions are split in 4 groups: 1. Program functions: Half Word and Word write. Get the read protection status 4. Call the desired function to erase page or program data. Call one or several functions to program the desired Option Bytes:.

NewState : new state of the Prefetch Buffer. Address : specifies the address to be programmed. Data : specifies the data to be programmed. Specifies the GPIO pins to be configured. Specifies the operating mode for the selected pins. Specifies the speed for the selected pins. Specifies the operating output type for the selected pins. In output mode, the speed is configurable: Low, Medium, Fast or High.

Peripherals alternate function:. The configuration of the locked GPIO pins can no longer be modified until the next reset. BitVal : specifies the value to be written to the selected bit.

This parameter can be one of the BitAction enumeration values:. PortVal : specifies the value to be written to the port output data register. This parameter can be one of the following value:.

Enables or disables analog noise filter. Configures the digital noise filter. Specifies the I2C mode. Specifies the device own address 1. Enables or disables the acknowledgement.

Specifies if 7-bit or bit address is acknowledged. Peripherals alternate function: DocID Rev 1. When using the DMA mode. Communications handling functions This section provides a set of functions that handles I2C communication.

In master mode, when transferring more than bytes Reload mode should be used to handle communication. In the first phase of transfer, Nbytes should be set to I2C registers management functions This section provides a functions that allow user the management of I2C registers. Data transfers management functions This subsection provides a set of functions allowing to manage the I2C data transfers. Interrupts and flags management functions This section provides functions allowing to configure the I2C Interrupts sources and check or clear the flags or pending bits status.

I2Cx : where x can be 1 or 2 to select the I2C peripheral. NewState : new state of the I2Cx peripheral. NewState : new state of the I2Cx Clock stretching. NewState : new state of the I2Cx stop mode. NewState : new state of the I2C own address 2. Inter-integrated circuit interface I2C Address : specifies the slave address to be programmed.

Mask : specifies own address 2 mask to be programmed. NewState : new state of the I2C general call mode. NewState : new state of the I2C slave byte control. Address : specifies the slave address to be programmed. NewState : new state of the I2C bit addressing mode. Enables or disables the I2C automatic end mode stop condition is automatically sent when nbytes data are transferred.

NewState : new state of the I2C automatic end mode. NewState : new state of the nbytes reload mode. NewState : new state of the I2C bit header only mode.

This mode can be used only when switching from master transmitter mode to master receiver mode. NewState : new state of the Acknowledge. This parameter must be a value between 0 and NewState : new state of the I2Cx clock Timeout. Timeout : specifies the TimeoutA to be programmed. Timeout : specifies the TimeoutB to be programmed.

Data : Byte to be transmitted.. When it reaches the end of count value 0x a system reset is generated. The measured value can be used to have an IWDG timeout with an acceptable accuracy.

How to use this driver This driver allows to use IWDG peripheral with either window option enabled or disabled. To do so follow one of the two procedures below. Window option is disabled:.

This parameter must be a number between 0 and 0x0FFF. Specifies the IRQ channel to be enabled or disabled. This parameter can be a value between 0 and The sub-priority is only used to sort pending exception priorities, and does not affect active exceptions. Lowest Preemption priority. Lowest Subpriority. Lowest hardware priority IRQn position. This interrupts priority is managed only with subpriority. This value must be a multiple of 0x Selects the inverting input of the operational amplifier.

Selects the non inverting input of the operational amplifier. This feature is used when calibration enabled or OPAMP's reference connected to the non inverting input. NewState : new state of the Vrefint output. PGA and Vout can't be selected as seconadry inverting input. OffsetTrimming : the selected offset trimming mode.

This parameter DocID Rev 1. The PVD is stopped in Standby mode. WakeUp pins are used to wakeup the system from Standby mode. These pins are forced in input pull down configuration and are active on rising edges.

Sleep mode: Cortex-M4 core stopped, peripherals kept running. Stop mode: all clocks are stopped, regulator running, regulator in low power mode Standby mode: VCORE domain powered off. Any peripheral interrupt acknowledged by the nested vectored interrupt controller NVIC can wake up the device from Sleep mode. Internal SRAM and register contents are preserved. The voltage regulator can be configured either in normal or low-power mode. Standby mode The Standby mode allows to achieve the lowest power consumption.

It is based on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. The voltage regulator is OFF. Auto-wakeup AWU from low-power mode The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt Auto-wakeup mode.

Comparator auto-wakeup AWU from the Stop mode. Configure the comparator to generate the event. NewState : new state of the access to the RTC and backup registers. NewState : new state of the WakeUp Pin functionality. When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop. Power control PWR mode.

By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. This flag indicates that the system was resumed from StandBy mode. Configure the System clock frequency and Flash settings. Enable the clock for the peripheral s to be used. Can be used also as RTC clock source. It is recommended to use the following software sequences to tune the number of wait states needed to access the Flash memory with the CPU frequency HCLK.

Peripheral clocks configuration functions This section provide functions allowing to configure the Peripheral clocks. Before to start using a peripheral you have to enable its interface clock. In this case, you have to select another source of the system clock then change the HSE state ex. You can tailor it depending on the HSE crystal used in your application. This parameter must be a number between 0 and DocID Rev 1. The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

In this case, you have to select another source of the system clock then stop the HSI. This function must be used only when the PLL is disabled. NewState : new state of the Clock Security System.

If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure Clock Security System Interrupt, CSSI , allowing the MCU to perform rescue operations. PA8 should be configured in alternate function mode. A switch from one clock source to another occurs only if the target clock source is ready clock stable after startup delay or PLL locked.

If a clock source which is not yet ready is. Reset and clock control RCC selected, the switch will occur when the clock source will be ready. The clock source used as system clock. The returned value can be one of the following values:. Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency for more DocID Rev 1.

The frequency returned by this function is not the real frequency in the chip. Otherwise, this function may return wrong result. The result of this function could be not correct when using fractional value for HSE crystal. This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters. Otherwise, any configuration based on this function will be incorrect.

This clock is derived from the PLL Clock. This clock is derived from the HSI or System clock. This clock is derived from the PLL output.

NewState : new state of the Backup domain reset. This parameter can be any combination of the following values: DocID Rev 1. This parameter must be set to a value lower than 0x1FFF. This parameter must be set to a value in the range. Specifies the RTC Date. If the Alarm Date is selected, this parameter must be set to a value in the range. A backup domain reset is generated when one of the following events occurs: 1. The system can also wake up from low power modes without depending on an external interrupt Auto-wakeup mode , by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. It is split into 2 programmable prescalers to minimize power consumption.

When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. All RTC registers are Write protected. In this mode, the calendar counter is stopped and its value can be updated. To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. To enable the RTC Wakeup interrupt, the following sequence is required:.

To enable the RTC Tamper interrupt, the following sequence is required:. The RTC Prescaler register is write protected and can be written in initialization mode only. NewState : new state of the write protection. Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset. NewState : new state of the RTC reference clock. NewState : new state of the Bypass Shadow feature. When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.

This parameter can be one of the following values :. This parameter can be one any value from 0 to 0x7FFF. This parameter can be a value from 0 to 0xFFF. There is no comparison on sub seconds for Alarm. Only SS[0] is compared. Only SS[] are compared. Real-time clock RTC are don't care in Alarm comparison. This parameter can be a value from 0x to 0xFFFF. NewState : new state of the WakeUp timer. This parameter can be one of the following:.

NewState : new state of the digital calibration Output. This parameter can be can be one of the following values:. This parameter can be one any value from 0 to 0xFF. NewState : new state of the TimeStamp. NewState : new state of the tamper pin. SS[14] is don't care in Alarm comparison. Specifies the SPI unidirectional or bidirectional data mode. Specifies the SPI data size. Specifies the serial clock steady state.

Serial peripheral interface SPI Specifies the clock active edge for the bit capture. Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. Specifies the I2S operating mode. Specifies the standard used for the I2S communication. Specifies the data format for the I2S communication. Specifies the frequency selected for the I2S communication. Specifies the idle state of the I2S clock. It is possible to use SPI in I2S full duplex mode, in this case, each SPI peripheral is able to manage sending and receiving data simultaneously using two data lines.

The extension block uses the same clock sources as its master. To configure I2S full duplex you have to:. In reception, data are received and then stored into an internal Rx buffer while In transmission, data are first stored into an internal Tx buffer before being transmitted.

It is advised to don't read the calculate CRC values during the communication. When the SPI is in slave mode, be careful to enable CRC calculation only when the clock is stable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be done.

With high bitrate frequencies, be careful when transmitting the CRC. This may happen for example in case of a multislave environment where the communication master addresses slaves alternately. Between a slave deselection high level on NSS and a new slave selection low level on NSS , the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation.

The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. Do not use the BSY flag to handle each data transmission or reception. The function calculates the optimal prescaler needed to obtain the most accurate audio frequency depending on the I2S clock source, the PLL values and the product DocID Rev 1.

Serial peripheral interface SPI configuration. But in case the prescaler value is greater than , the default value 0x02 will be configured instead. NewState : new state of the SPIx peripheral.

For the SPIx peripheral this parameter can be one of the following values:. I2Sxext : where x can be 2 or 3 to select the I2S peripheral extension block. In this case, if the master is configured as transmitter, the slave will be receiver and vice versa.

The I2S full duplex extension can be configured in slave mode only. NewState : new state of the NSS pulse management mode. When TI mode is selected, the control bits NSSP is not taken into consideration and are configured by hardware respectively to the TI mode requirements. Data : Data to be transmitted. This parameter can be: Enable or Disable. NewState : new state of the mapping of USB interrupt lines. Disabling the parity check on RAM locks the configuration bit. To re-enable the parity check on RAM perform a system reset.

Specifies the prescaler value used to divide the TIM clock. Specifies the counter mode. Specifies the period value to be loaded into the active Auto-Reload Register at the next update event.

This parameter must be a number between 0x and 0xFFFF. Specifies the clock division. Specifies the repetition counter value. Specifies the TIM mode. Specifies the pulse value to be loaded into the Capture Compare Register. Specifies the output polarity. Specifies the complementary output polarity.

Specifies the TIM channel. Specifies the active edge of the input signal. Specifies the input. Specifies the Input Capture Prescaler. Specifies the Off-State selection used in Run mode. Specifies the Off-State used in Idle state. Specifies the LOCK level parameters. Specifies the delay time between the switching-off and the switching-on of the outputs. Specifies whether the TIM Break input is enabled or not.

All other functions can be used separately to modify, if needed, a specific feature of the Timer. How to use this driver This driver provides functions to configure and program the TIM of all stm32f30x devices. These functions are split in 9 groups: 1.

TIM clocks management: this group includes all needed functions to configure the clock controller unit:. TIM synchronization management: this group includes all needed functions to configure the Synchronization unit:. ETR Configuration when used as external trigger 8. TIM specific interface management, this group includes all needed functions to use the specific TIM interface:. Counter : specifies the Counter register new value.

Autoreload : specifies the Autoreload register new value. NewState : new state of the TIMx peripheral. This function disables the selected channel before changing the Output Compare Mode. Compare1 : specifies the Capture Compare1 register new value. Compare2 : specifies the Capture Compare2 register new value. Compare3 : specifies the Capture Compare3 register new.

Compare4 : specifies the Capture Compare4 register new value. Compare5 : specifies the Capture Compare5 register new value.

Compare6 : specifies the Capture Compare5 register new value. This parameter must be a value between 0x00 and 0x0F. NewState : new state of the TIM interrupts. This parameter can be one or more of the following values:. This parameter must be a DocID Rev 1.

UM peripheral. Specifies the number of data bits transmitted or received in a frame. Specifies the number of stop bits transmitted. Specifies the parity mode. Specifies wether the Receive or Transmit mode is enabled or disabled.

Universal synchronous asynchronous receiver transmitter USART Specifies wether the hardware flow control mode is enabled or disabled. Specifies the steady state of the serial clock. Specifies the clock transition on which the bit capture is made. Specifies whether the clock pulse corresponding to the last transmitted data bit MSB has to be output on the SCLK pin in synchronous mode. Peripheral's alternate function:. When using the DMA mode:.

Initialization and Configuration functions This subsection provides a set of functions allowing to initialize the USART in asynchronous and in synchronous modes. Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit 8-bits or 9-bits , the possible USART frame formats are as listed in the following table: M bit.

For the synchronous mode in addition to the asynchronous mode parameters these parameters should be also configured:. RS flow control Driver enable feature handling is possible through the following procedure: 1. Interrupts and flags management functions This subsection provides a set of functions allowing to configure the USART Interrupts sources, Requests and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode.

Pending Bits: a. Interrupt Source: a. These function take as parameter : 1. USART multiprocessor communication is possible through the following procedure:. In LIN mode, the following bits must be kept cleared:.

The RX pin is no longer used. The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO standard. In smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. Smartcard communication is possible through the following procedure: 1. Please refer to the ISO specification for more details.

It is also possible to choose 0. IrDA is a half duplex communication protocol. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. IrDA communication is possible through the following procedure: 1. A pulse of width less than two and greater than one PSC period s may or may not be rejected. The receiver set up time should be managed by software.

The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception IrDA is a half duplex protocol.

The parity bit is also inverted. NewState : new state of the driver enable mode. Data : the data to transmit.

NewState : new state of the Smart Card mode. NewState : new state of the IrDA mode. WWDG features Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter downcounter before to reach 0x3F value i. An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window.

Once enabled the WWDG cannot be disabled except by a system reset. When the WWDG is enabled the counter value should be configured to a value greater than 0x40 to prevent generating an immediate reset. Optionally you can enable the Early wakeup interrupt which is generated when the counter reach 0x Once enabled this interrupt cannot be disabled except by a system reset.

WindowValue : specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x Counter : specifies the watchdog counter value.

This parameter must be a number between 0x40 and 0x7F to prevent generating an immediate reset. Please Read Carefully Information in this document is provided solely in connection with ST products.

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Information in this document supersedes and replaces all information previously supplied. All other names are the property of their respective owners. Pular no carrossel. Anterior no carrossel. UM User Manual. Enviado por Mike Empey. Denunciar este documento. Fazer o download agora mesmo. Salvar Salvar UM User manual para ler mais tarde. Pesquisar no documento.

The firmware library user manual is structured as follows: Document conventions, rules, architecture and overview of the Library package. Table 2: List of abbreviations 1. Coding rules This section describes the coding rules used in the library.

General All codes should comply with ANSI C standard and should compile without warning under at least its main compiler. Complexity Needed when addressing memory mapped registers CMSIS layer Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to access core registers and peripherals. Z, which contains the following subfolders: Figure 2: Library package structure 1.

Z refer to the library version, ex. They do not need to be modified by the user: inc subfolder contains the peripheral drivers header files. This file contains: Configuration section allowing: To select the device used in the target application To use or not the peripheral drivers in your application code meaning that the code is based on direct access to peripheral registers rather than drivers API.

Refer to the library release notes to know about the supported development tool version. Figure 6: Message displayed on the LCD when running the template example 2.

It gives a real example based on the requirements described below: 2. This parameter can be a value between 0x0 and 0xF 3. This section provide functions allowing to configure the ADC Injected channels, it is composed of 2 sub sections : Configuration functions for Injected channels: This subsection provides functions allowing to configure the ADC injected channels : 3.

Return values None. Notes None. Parameters 3. Notes : Channel 15, 16 and 17 are fixed to single-ended inputs mode. Parameters UM 3. Return values The Data conversion value. Notes In dual mode, the value returned by this function is as following Data[] : these bits contain the regular data of the Master ADC. UM Return values None. Notes 3. It ranges from 0 to 0xFF. Parameters 4. Mailbox : Mailbox number. Return values NbMessage : which is the number of pending message.

Notes In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. Notes If the selected comparator is locked, initialization can't be performed. UM 5. Parameters NewState : New state of the analog switch. This switch is solely intended to redirect signals onto high impedance input, such as COMP1 non-inverting input highly resistive switch 5.

Notes Locking the configuration means that all control bits are readonly. Parameters None. Parameters NewState : new state of the reverse operation on output data. Return values 8-bit value of the ID register Notes None. Parameters 7. Notes When the DAC channel is enabled the trigger source can no more be modified. Notes In dual mode, a unique register access is required to write in both DAC channels at the same time.

Parameters Return values None. Notes The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received first request. Return values Device revision identifier Notes None. Return values Device identifier Notes None. This counter is decremented at the end of each data transfer and when the transfer is complete: If Normal mode is selected: the counter is set to 0.

The following function can be used to read the Channel data counter value: 9. Parameters 9. Notes Erase function: Erase page, erase all pages. Get flags status. Clear flags. UM Parameters NewState : new state of the Prefetch Buffer. UM Notes Parameters Address : specifies the address to be programmed. Parameters UM Address : specifies the address to be programmed.

Return values The input port pin value. Return values The output port pin value. Parameters Parameters BitVal : specifies the value to be written to the selected bit. Pending Bits: 1. Parameters I2Cx : where x can be 1 or 2 to select the I2C peripheral. Notes This function should be called before generating start condition.

Notes This function has effect if Reload mode is disabled. Notes This mode can be used only when switching from master transmitter mode to master receiver mode. Notes UM Return values The value of the slave matched address. Return values The value of the received request. Return values The value of the PEC.

Return values The value of the read register. Data transfers management functions Return values The value of the received data. DMA transfers management functions Interrupts and flags management functions Parameters WindowValue : specifies the window value to be compared to the downcounter.

Lower priority values gives higher priority. Priority Order: 1. Parameters UM Return values None. Parameters NewState : new state of the Vrefint output. Parameters OffsetTrimming : the selected offset trimming mode. Exit: Any peripheral interrupt acknowledged by the nested vectored interrupt controller NVIC can wake up the device from Sleep mode.

Once the device starts from reset, the user application has to: Notes The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. Notes This function must be used only when the PLL is disabled. Notes PA8 should be configured in alternate function mode. Return values The clock source used as system clock.

Parameters NewState : new state of the Backup domain reset. A 7-bit asynchronous prescaler and A bit synchronous prescaler. Parameters NewState : new state of the write protection. Parameters NewState : new state of the Bypass Shadow feature.

Notes When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter. Backup Data Registers configuration functions Output Type Config configuration functions Time and Date configuration functions Alarm configuration functions Notes This function is performed only when the Alarm is disabled. WakeUp timer configuration functions Parameters NewState : new state of the WakeUp timer. Daylight saving configuration functions Output pin configuration functions Parameters NewState : new state of the digital calibration Output.

Timestamp configuration functions Return values RTC current timestamp Subseconds value. Tamper configuration functions Notes The timestamp is valid even the TSE bit in tamper control register is reset. Parameters NewState : new state of tamper pull up. To clear the CRC, follow the procedure below: 1.

Interrupt Source: 1. Parameters I2Sxext : where x can be 2 or 3 to select the I2S peripheral extension block. Notes The selected configuration is locked and can be unlocked by system reset Notes Disabling the parity check on RAM locks the configuration bit. Return values Counter Register value Notes None. Return values Prescaler Register value. Notes This function disables the selected channel before changing the Output Compare Mode. Input Capture management functions Return values Capture Compare 1 Register value.

Return values Capture Compare 2 Register value. Return values Capture Compare 3 Register value. Return values Capture Compare 4 Register value. This parameter must be a value between 0x00 and 0x0F Return values None.

Interrupts DMA and flags management functions